The present invention relates to an extended memory address control system.
Supercomputers have arithmetic processing speeds much higher than that of general computers, and can solve various equations expressing natural phenomena using a large volume of data at high speed for a variety of studies and technical developments in scientific and technical fields.
For example, if a crush test of vehicle bodies by a vehicle manufacturer can be simulated using a supercomputer, the number of vehicles used in a test can be decreased. An aircraft manufacturer employs a supercomputer to analyze air vortices formed around wings which have been tested using a wind tunnel.
In a supercomputer which conducts large-scale scientific technical calculations, the scale of a problem as an object to be calculated is also increased, and a huge volume of data is necessary.
Therefore, a large amount of data is stored in a secondary memory such as a magnetic disk device. Thus, calculations are executed while inputting/outputting data between the magnetic disk device and a main memory. Therefore, an input/output (I/O) time between the secondary and main memories greatly influences performance of the entire program. Thus, the supercomputer has an extended memory to increase an I/O speed.
A supercomputer of this type comprises a system controller, an I/O processor connected thereto, a control processor, a high-speed arithmetic processor, a first main memory, a second main memory, and an extended memory.
The control processor has a supervisor function, and realizes I/O control, and a compiler and a linker for user programs. The first main memory stores a control program for controlling the control processor.
The second main memory stores load modules of the user programs, and data. The high-speed arithmetic processor executes the user programs.
The I/O processor controls data transfer between peripheral devices such as a magnetic disk, and the first main memory.
The I/O processor, the control processor, and the high-speed arithmetic processor can be operated independently of each other, thus improving a throughput of the system.
Data transfer between the extended memory and the second main memory is controlled by commands on the high-speed arithmetic processor.
Data transfer between the extended memory and the first main memory is controlled by commands on the control processor.
In a conventional information processing apparatus of this type, an extended memory is managed as a virtual disk for a user to increase an I/O speed.
However, since a buffer size is extended to increase a hit rate and to decrease the number of I/O times in order to increase a database access speed, a large buffer must be allocated to the extended memory since the main memory has a limited memory size.
In this case, if the extended memory is managed as the virtual disk, since it has discontinuous address spaces, an overhead of managing address spaces is increased when a large-sized buffer is to be allocated. Thus, an address management module must be called at many positions of an operating system for each access, thus impairing performance.
In the conventional supercomputer, since addresses of the extended memory are managed as the virtual disk addresses, they cad,not be recognized as continuous addresses on the operating system. Thus, backing store I/Os frequently occur since a large logical space is used when a buffer having a large number of continuous addresses is prepared in the extended memory to increase a database access speed. When the extended memory is utilized as a paging backing store, a swapping backing store, or their caches to improve performance of the system or to shorten a TSS (Time Sharing System) response time, or when a file on a disk is mapped on a logical space to access the file by a transfer command. Thus, when the extended memory is used as a backing store to improve performance, an overhead of managing address spaces is increased. As a result, as the number of access times of the extended memory is increased, access performance is impaired.